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? semiconductor components industries, llc, 2013 march, 2013 ? rev. 0 1 publication order number: EMI4162MU/d EMI4162MU common mode filter with esd protection functional description the EMI4162MU is an integrated common mode filter providing both esd protection and emi filtering for high speed digital serial interfaces such as hdmi or mipi d-phy. the EMI4162MU provides protection for two differential data line pairs in a small rohs-compliant udfn10 package. features ? highly integrated common mode filter (cmf) with esd protection provides protection and emi reduction for systems using high speed serial data lines with cost and space savings over discrete solutions ? large differential mode bandwidth with cutoff frequency > 2 ghz ? high common mode stop band attenuation: >25 db at 700 mhz, >30 db at 800 mhz ? provides esd protection to iec61000-4-2 level 4, 15 kv contact discharge ? low channel input capacitance provides superior impedance matching performance ? low profile package with small footprint in udfn10 2 x 2.5 mm pb ? free package ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? hdmi/dvi display in mobile phones ? mipi d-phy (csi-2, dsi, etc) in mobile phones and digital still cameras 1 2 4 5 10 9 7 6 3, 8 (connector) (asic) figure 1. EMI4162MU electrical schematic external internal udfn10 case 517cj marking diagrams http://onsemi.com 62 = specific device code m = date code = pb ? free package (*note: microdot may be in either location) 1 2 4 5 10 9 7 6 in_1+ in_1 ? out_1+ out_1 ? in_2+ in_2 ? out_2+ out_2 ? 38 gnd gnd pin connections device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. EMI4162MUtag udfn10 (pb ? free) 3000/tape & reel 62m
EMI4162MU http://onsemi.com 2 pin function description pin name pin no. type description in_1+ 1 i/o cmf channel 1+ to connector in_1 ? 2 i/o cmf channel 1 ? to connector out_1+ 10 i/o cmf channel 1+ to asic out_1 ? 9 i/o cmf channel 1 ? to asic in_2+ 4 i/o cmf channel 2+ to connector in_2 ? 5 i/o cmf channel 2 ? to connector out_2+ 7 i/o cmf channel 2+ to asic out_2 ? 6 i/o cmf channel 2 ? to asic v n 3, 8 gnd ground absolute maximum ratings (t a = 25 c unless otherwise noted) parameter symbol value unit operating temperature range t op ? 40 to +85 c storage temperature range t stg ? 65 to +150 c esd discharge iec61000 ? 4 ? 2 contact discharge v pp 15 kv maximum lead temperature for soldering purposes (1/8? from case for 10 seconds) t l 260 c dc current per line i line 100 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter test conditions min typ max unit i leak channel leakage current t a = 25 c, v in = 5 v, gnd = 0 v 1.0 a v f channel negative voltage t a = 25 c, i f = 10 ma 0.1 1.5 v c in channel input capacitance to ground (pins 1, 2, 4, 5 to pins 3, 8) t a = 25 c, at 1 mhz, gnd = 0 v, v in = 1.65 v 0.8 1.3 pf r ch channel resistance (pins 1 ? 10, 2 ? 9, 4 ? 7 and 5 ? 6) 8.0 f 3db differential mode cut ? off frequency 50 source and load termination 2.0 ghz f atten common mode stop band attenuation @ 800 mhz 30 db v esd esd protection ? peak discharge voltage at any channel input, in system: contact discharge per iec61000 ? 4 ? 2 standard t a = 25 c (notes 1 and 2) pins 1, 2, 4, 5 15 kv v cl tlp clamping voltage (see figure 12) forward i pp = 8 a forward i pp = 16 a forward i pp = ? 8 a forward i pp = ? 16 a 12 18 ? 6 ? 12 v v v v r dyn dynamic resistance positive transients negative transients t a = 25 c, i pp = 1 a, t p = 8/20 s any i/o pin to ground; notes 1 and 3 1.36 0.6 v rwm reverse working voltage (note 3) 5.0 v v br breakdown voltage i t = 1 ma; (note 4) 5.6 9.0 v 1. standard iec61000 ? 4 ? 2 with c discharge = 150 pf, r discharge = 330, gnd grounded. 2. these measurements performed with no external capacitor. 3. tvs devices are normally selected according to the working peak reverse voltage (v rwm ), which should be equal to or greater than the dc or continuous peak operating voltage level. 4. v br is measured at pulse test current i t .
EMI4162MU http://onsemi.com 3 typical characteristics figure 2. differential mode attenuation vs. frequency (zdiff = 100 ) figure 3. common mode attenuation vs. frequency (zcomm = 50 ) figure 4. differential return loss vs. frequency (zdiff=100 ) figure 5. differential inter ? lane cross ? coupling figure 6. common mode inter ? lane cross ? coupling 1e6 1e7 1e8 1e9 1e5 6e9 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 ? 40 0 frequency, hz db (scc21) 1e6 1e7 1e8 1e9 1e5 6e9 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 ? 40 0 frequency, hz db(sdd11) db(sdd22) 1e6 1e7 1e8 1e9 1e5 6e9 ? 7 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 ? 9 0 frequency, hz db (scc21) ? 8
EMI4162MU http://onsemi.com 4 mipi dsi (d ? phy) host client EMI4162MU evaluation board mipi dsi (d ? phy) figure 7. mipi d ? phy lp mode test setup figure 8. EMI4162MU mipi d ? phy lp mode measured results
EMI4162MU http://onsemi.com 5 figure 9. EMI4162MU eye diagram test setup EMI4162MU figure 10. EMI4162MU measured eye diagram @ 3.4gbps (evb through on left, evb with emi4162 on right)
EMI4162MU http://onsemi.com 6 transmission line pulse (tlp) measurements transmission line pulse (tlp) provides current versus voltage (i-v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 11. tlp i-v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10 s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 12 where an 8 kv iec61000-4-2 current waveform is compared with tlp current pulses at 8 and 16 a. a tlp curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. typical tlp i-v curves for the emi4162 are shown in figure 13. figure 11. simplified schematic of a typical tlp system dut v m i m l 10 m v c sw oscilloscope attenuator 50 coax cable 50 coax cable figure 12. comparison between 8 kv iec61000 ? 4 ? 2 and 8 a and 16 a tlp waveforms figure 13. positive and negative tlp waveforms
EMI4162MU http://onsemi.com 7 esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconduct or has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to on semiconductor application notes and8307/d and and8308/d. iec61000 ? 4 ? 2 spec. level test voltage (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns 50 50 cable tvs oscilloscope esd gun figure 14. diagram of esd test setup figure 15. 8 x 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 020406080 t, time ( s) % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s
EMI4162MU http://onsemi.com 8 figure 16. esd clamping voltage +8 kv per iec6100 ? 4 ? 2 (external to internal pin) figure 17. esd clamping voltage ? 8 kv per iec6100 ? 4 ? 2 (external to internal pin)
EMI4162MU http://onsemi.com 9 110 110 tmds data 2+ tmds data 2 ? tmds data 1+ tmds data 1 ? tmds data 0+ tmds data 0 ? tmds clock+ tmds clock ? scl +5v power hot plug detect cec sda nup4114 emi4162 emi4162 scl 5v cec gnd d0 ? gnd d0 + d2 ? d2 + htp _d gnd sda clk ? clk + gnd d1 + d1 ? gnd hec data black = top layer red = other layer hdmi type ? a connector figure 18. emi4162 hdmi type ? a connector application diagram pin 1 scl 5v cec gnd d0 ? gnd d0 + d2 ? d2 + htp _d gnd sda clk ? clk + gnd d1+ d1 ? gnd util 110 110 tmds data 2+ tmds data 2 ? tmds data 1+ tmds data 1 ? tmds data 0+ tmds data 0 ? tmds clock + tmds clock ? cec scl +5v power sda nup4114 emi4162 emi4162 hdmi type ? d connector black = top layer red = other layer figure 19. emi4162 hdmi type ? d connector application diagram
EMI4162MU http://onsemi.com 10 package dimensions ??? ??? ??? case 517cj issue o dim min max millimeters a a1 0.00 0.05 a3 b 0.15 0.25 d 2.50 bsc e 2.00 bsc e 0.50 bsc notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimensions b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 0.13 ref b l pin one 1 6 5 d e b a c 0.10 c 0.10 2x 2x 10 e 8x 9x note 3 a note 4 c a1 (a3) seating plane c 0.05 c 0.05 0.45 0.55 l 0.70 0.90 reference top view side view bottom view 0.30 1.07 2.30 0.50 pitch dimensions: millimeters mounting footprint* 8x 1 recommended detail a b a c c m 0.10 m 0.05 0.10 l1 0.05 0.15 detail b min 8x 0.45 package outline l1 detail a l alternate terminal constructions l ?? ?? ?? *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 EMI4162MU/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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